Hint:
generally it is to recommend, to use syscalls instead of directly accessing
registers, if possible.
The GetDeviceInfo-function of protocol 7.00 returns RENESAS SH730501 as processor identifier.
The protocol 7.00 Get Device Info-function (01) works as expected.
HardwareIdentifier: Ly755000
ProcessorIdentifier: RENESAS SH730501
PreprogrammedROMcapacity: 00000000
FlashROMcapacity: 00032768
RAMcapacity: 00002048
PreprogrammedROMversion:
Bootcodeversion:
Bootcodeoffset:
Bootcodesize:
OScodeversion: 01.02.0200
OScodeoffset: 00020000
OScodesize: 00012288
Protocolversion: 7.00
ProductID1: returns the individual calculator-ID
ProductID2:
NamesetbyuserinSYSTEM:
Probably it is a customized SH
7705/7720/7730/7724-clone.
The SH 7724 has been mentioned first by brijohn (http://cemetech.net/forum/viewtopic.php?t=5507&start=156).
Th SH 7724 is the closest match to the 7305, though the SH 7724 obviously
contains no ADC.
The serial-registers are similar to these of the 7705, but obviously not identical.
Syscall 0x1BB4 uses a TMU with the base address
0xA4490004, which is neither 7705 nor 7720.
The register structure is identical to the 7730 TMU.
| Module | 7305 (Prizm/GII-2) | 7705 | 7720 | 7724(*5) | 7730 | 7337 (G) | 7355 (GII) | |
| RTC | A413 FEC0 | FFFF FEC0 | A413 FEC0 | A465 FEC0 | A465 FEC0 | FFFF FEC0 | ||
| DMAC | FE00 8020 | A400 0020 | A401 0020 | FE00 8020 | FE00 8020 | A400 0020 | ||
| ADC | A461 0080 | A400 0080 | A44C 0000 | - | A461 0000 | A400 0080 | ||
| TMU | A449 0004 | FFFF FE92 | A412 FE92 | FFD8 0004 | FFD8 0004 | FFFF FE92 | ||
| X/Y-memory (16 k) | - | A5007000(8k)/A5017000(8k) | A560 0000 | A560 0000 | ||||
| RS-memory (16 k) | FD80 0000 | - | FD80 0000 | - | ||||
| IL-memory (16 k) | E520 0000(*2) | A500 7000/A501 7000 | E520 0000 | E520 0000 | A560 0000 | |||
| UBC | FF20 0000 | FFFF FF90 | A4FF FF90 | FF20 0000 | FF20 0000 | FFFF FF90 | ||
| SCIF | A441 0000(*1) | A441 0000 | A443 8000 | FFE0 0000 | FFE0 0000 | A441 0000 | ||
| STBCR | A415 0020 | FFFF FF82 | A415 FF82 | A415 0020 | A415 0020 | FFFF FF82 | ||
| MSTPCR0 | A415 0030 | A415 FF88 | A415 0030 | A415 0030 | ||||
| INTEVT | FF00 0028 | FFFF FFD8 | FFFF FFD8 | FF00 0028 | FF00 0028 | FFFF FFD8 | ||
| PLLCR | A415 0024(*3) | A415 0024 | A415 0024 | |||||
| FRQCR | A415 0000(*4) | A415 0000 | A415 0000 | |||||
| PACR | A4050100 | A4000100 | A4050100 | A4050100 | A4050000 | A4000100 | ||
| PADR | A4050120 | A4000120 | A4050120 | A4050120 | A4050080 | A4000120 | ||
| EXTRA TMU | A44D0000 | - | - | - | - | A44C0030 | A44C0030 | |
| KEYSC | A44B0000 | - | - | A44B0000 | - | - | ||
| PVR return value | 10300B00 | 10300B00 | ||||||
| PRR return value | 00002C00 | - | - | 00002200 | - | |||
| IMR9 | A408 00A4 | A408 00A4 | A408 00A4 | |||||
| USB mask bit | IMR9.1 | IMR9.1 | - | |||||
| BCD ALU | A4CB0010..18 | A44C0010..18 | A44C0010..18 | |||||
(*1): address of the 7705, register structure of 7730.
(*2): the 7305 has at least one additional On-Chip-RAM-area: 2x8k at
E5007000..E5008FFF/E5017000..E5018FFF.
(*3): address of the 7730, register structure of 7780.
(*4): address of the 7730, register structure unknown.
(*5): found by brijohn (http://cemetech.net/forum/viewtopic.php?t=5507&start=156)
XXXX:
compatible, different address
XXXX: identical address,
incompatible
XXXX: compatible, identical
address
The processor version register 0xFF000030 of the Prizm
returns 0x10300B00.
According to the 7450/7451 hardware manual, appendix D, a CHIP-version code "is
always "H'10" in the SH-4A".
The major version byte (VER) is 0x30.
The minor version byte (CUT) is 0x0B.
The product version register 0xFF000044 of the Prizm returns 0x00002C00.
These return values are the same with the fx-9860GII-2 processor.
The standard 7730 does not contain an USB-module!
| MPU | USB-base | USB-clock control | USB-transceiver control | |
| 7124/7125 | none | |||
| 7205 | FFFF 0000 | |||
| 7705 | A448 0000 | |||
| 7710 | none | |||
| 7720 | A442 0000/A442 8000 | A40A 0008 | A405 012C | |
| 7724 | A4D8 0000 | |||
| 7727 | 0400 0240/0400 0400 | |||
| 7730 | none | |||
| 7750/7751 | none | |||
| 7760 | FE34 0000 | |||
Available information about the 7305-USB-module:
Uses bit 1 of 7730-IMR09 and 7730-IMCR09 to mask the USB-interrupt (which is
the documented scheme on the 7724).
Available information about the 7305-Ports:
(Hint: some of the ports are used by the system.
Writing them lightheadedly may lead to a crash)
| Adress (CR) | Adress (DR) | Special remarks | direction | |
| A4050100 | A4050120 | System. Take care. | ||
| A4050102 | A4050122 | |||
| A4050104 | A4050124 | |||
| A4050106 | A4050126 | |||
| A4050108 | A4050128 | |||
| A405010A | A405012A | |||
| A405010C | A405012C | |||
| A405010E | A405012E | |||
| A4050110 | A4050130 | bit 3 is
connected to the serial-receive-pin bit 2 is connected to the serial-transmit-pin |
I O |
|
| A4050112 | A4050132 | |||
| A4050114 | A4050134 | bit 2 is connected to the serial-receive-pin | I/O | |
| A4050116 | A4050136 | keyboard injector 1 control/data | O | |
| A4050118 | A4050138 | bits 0..3: keyboard injector 2 control/data | O | |
| A4050118 | A4050138 | bit 4: LCD enlighten | I/O | |
| A405011A | A405013A | |||
| A405011C | A405013C | |||
| A405011E | A405013E | |||
| A4050140 | A4050160 | |||
| A4050142 | A4050162 | bit 3 enables the serial output gate | O | |
| A4050144 | A4050164 | |||
| A4050146 | A4050166 | |||
| A4050148 | A4050168 | |||
| A405014A | A405016A | |||
| A405014C | A405016C | keyboard detector control/data | I | |
| A405014E | A405016E | |||
| A40501C6 | keyboard | |||
Accessing the 3pin serial lines directly:
Always ensure, that the other pins and pin-functions of
a port are never changed.
Always ensure to restore the original state of pins and pin-functions.
As long as the serial
pin-functions are not restored to the original state, any attempt to
communicate serially will fail.
For general aspects of programming the pin function
controller (PFC) refer to the 7730-hardware manual. Though the 7305 pin
functions are not compatible to those of the 7730 (as well as to any other
SH-3 or SH-4 processor).
A very close match seem to be the registers of the SH 7724. Alas this is under
NDA.
At first the outer gate has to be opened:
Set bit 3 of SH-7724 port U 0xA4050162 to output mode, t. i. set control
register 0xA4050142 accordingly.
Set bit 3 and bit 2 of SH-7724 port U 0xA4050162. Do not ask why bit 2 has to
be set, too. I do not know.
How to control the output of the serial transmit pin:
Set bit 2 of SH-7724 port J 0xA4050130 to output mode, t. i. set control
register 0xA4050110 accordingly.
Set or clear bit 2 of SH-7724 port J 0xA4050130 to control the serial transmit
pin state.
How to read the state of the serial receive pin:
Set bit 3 of SH-7724 port J 0xA4050130 to input mode, t. i. set control
register 0xA4050110 accordingly.
Read SH-7724 port J 0xA4050130 and isolate bit 3 to obtain the serial receive
pin state.
(see Insight's F17_Handler's source as reference)
(13.10.2012 16:46:43)