The legacy systems are 7705-based. The identification of the customized processors is 7337(G) and 7355(GII), resp..
The BCD-arithmetic-registers are not documented in the
7705 hardware manual.
Perhaps a customized processor enhancement (7337; with OS 2.00 the ID has been changed to 7355) or a separate piece of hardware.
The BCD-unit is able to add or subtract two 8-digit (32 bits) BCD-numbers.
A44C0014, 32bit, BCD operand 1
A44C0018, 32bit, BCD operand 2
A44C0010, 16bit, command and status
A44C001C, 32bit, BCD result
write a value to operand 1
write a value to operand 2
write a command
read the result
typical addition sequence of two 24 digit BCD values at 0x80013E00, OS 1.03.
typical subtraction sequence of two 24 digit BCD values at 0x80013EEE, OS 1.03.
the following command-bits are known:
bit 0: 1=add, 0=subtract
bit 1: 1=use carry of the previous operation, 0=do not
bit 2: 1=use carry in any case, 0=do not
the following status-bits are known:
bit 12: carry of the previous operation
A44C0030, A44C0034, A44C0038, A44C003C are registers of
an extra timer, which is used to serve the 10
software timers. It works like a TMU (downcounting). The low nibble of
IRPF is assigned to this timer's interrupt. According to the 7705 manual this
nibble is reserved, but it matches with the 7720's Compare Match Timer (CMT).
The 7705 embedded CMT does not support interrupts.
syscall 3f7 is the interrupt handler (int code 0xF00; corresponds to the CMT INT source ID of the 7720 and the 7366.)
It scans the 10 timers and calls the handlers, if active and assigned.
If no software timers is active, it disables the extra TMU's interrupts.
A44C0030: timer start register (8), bit 0 = 1 starts the timer.
A44C0034: timer constant register (16)
A44C0038: timer counter (16)
A44C003C: timer control/status register (8), bit 1 is waited for in some situations.
This timer is running permanently as long as a software timers is active. F. i. it runs when the calc waits for a key to be pressed or on the slim when backlight is switched on.
Some registers in the range A45500XX are involved during
SD-card access (together with the DMAC).
At least 0xA4550000.w,
0xA4550004.w to 0xA4550028.w,
0xA4550030.l to 0xA455003C.l,
0xA45500D8.w, 0xA45500E0.w and 0xA45500F0.w are used in the OS.
Most probably a SDHI, perhaps a MMCIF. Though, the MMCIF-register-structure is not the same as on other MPUs, which contain a MMCIF as standard (f. i. 7720 or 7780). SDHI is explicitly excluded from documentation by renesas throughout all hardware manuals by nondisclosure-agreements.
The DMA Extended Resource Selector MID is B'11000001/10 (h'C1/h'C2) for DMARS0 for the SDHI/MMCIF. This corresponds to the SDHI MIDs of the 7720.
The INT source ID is h'E80 for the SDHI/MMCIF. This corresponds to the SDHI INT source ID of the 7366.
0xA4550030 is set to the DMA Source/Destination Address Register SAR0/DAR0 when setting up the DMAC for a transfer.
On the 7720 the SDHI-pins are shared with port U (A4050120/A4050160).
In the A44CXXXX-hardware-register-address-range the
address-bits 7..15 obviously are not decoded.
The following registers are used, too. Their function is unknown yet.
A44C0008.b: set to 0x40 (0x80001D92, OS 1.03)
A44C0020.b: bit 2 is cleared (0x80001044, 0x80001072, 0x80004E2C, OS 1.03)
A44C0020.b: bit 2 is set (0x8000115A, OS 1.03)
A44C0020.b: set to 0x00 (0x80001AC2, OS 1.03)
A44C0024.w: set to 0xC000 (0x80001048, OS 1.03)
A44C0026.b: set to 0x20 (0x8000104C, 0x80001D8A, OS 1.03)